A quadrature clock correction circuit is used in a transmitter to compensate for duty cycle error and phase mismatch of the input clock signals. To overcome process, voltage, and temperature (PVT) variations, the calibration scheme implemented by a quadrature clock correction circuit can be either foreground calibration or background calibration. The former provides one-round correction after being turned on, whereas the latter keeps tracking the temperature and supply variations. Without the quadrature clock correction circuit, any timing error between the in-phase and the quadrature-phase clocks will lead to much larger jitter in subsequent stages of the transmitter.
One type of quadrature clock correction circuit divides the correction process into two independent stages. One stage minimizes in-phase/quadrature-phase (IQ) mismatch. The other stage corrects the duty cycle of the IQ phase-corrected clocks. The two-stage structure results in larger power consumption. The IQ phase-correction stage typically employs a variable capacitor at the output to adjust the time delay. The duty cycle correction stage typically employs a resistor array to adjust output rise time and fall time in order to correct duty cycle error. As a result, power consumption is increased due to the internal loading of these techniques.
It is desirable to provide a quadrature clock correction circuit that minimizes power consumption.